(1) Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory, (DRAM), cell, on a semiconductor substrate.
(2) Description of Prior Art
The ability to continually increase the signal of DRAM devices, via capacitance increases, using a stacked capacitor configuration, is limited by the dimension of the underlying transfer gate transistor. The reduced dimensions of the underlying transfer gate transistor limit the amount of capacitor area available for an overlying stacked capacitor structure, thus motivating semiconductor device designers, and process engineers, to migrate to DRAM cells, incorporating trench capacitors. The ability to create the DRAM capacitor in a trench in the semiconductor substrate, has allowed DRAM devices densities of 64 Mbit and greater to be achieved.
This invention will offer a fabrication sequence used for the creation of high density DRAM designs, using a two dimensional trench capacitor structure. The use of a silicon on insulator, (SOI), layer, incorporated in this invention, allows an undercutting of the trench to occur, in the region in which the trench resides in the insulator layer, underlying the SOI layer, resulting in an increase in capacitor surface area, for a specific trench depth. In addition the storage node capacitor layer, residing on the sides of the trench, shorts the SOI layer to the semiconductor substrate, thus eliminating a floating body effect that can occur with DRAM structures, fabricated in on a SOI layer. Prior art such as Tang, U.S. Pat. No. 5,585,285, shows a trench through an SOI layer, but does not show the intentional undercut used in this invention, offering additional capacitor surface area. Ohtsuki, et al, in U.S. Pat. No. 5,629,226, describe a DRAM device, using a trench capacitor, with the bottom of the trench widened using diffusion procedures. However none of these prior arts describe a DRAM device, using the combination of a lateral undercut in a trench, and the elimination of the floating body effect resulting from the shorting of the SOI layer and the semiconductor substrate, via use of a storage node capacitor layer.